drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits

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Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Tom St Denis 2020-06-11 07:54:13 -04:00 • committed by Alex Deucher

parent 651a146526

commit 8d7fb7a10a

10 changed files with 109 additions and 5 deletions

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3

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h

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drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

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