drm/i915/dsi: fix DSS CTL register offsets for TGL+

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commit 6b8446859c upstream.

On TGL+ the DSS control registers are at different offsets, and there's
one per pipe. Fix the offsets to fix dual link DSI for TGL+.

There would be helpers for this in the DSC code, but just do the quick
fix now for DSI. Long term, we should probably move all the DSS handling
into intel_vdsc.c, so exporting the helpers seems counter-productive.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230301151409.1581574-1-jani.nikula@intel.com
(cherry picked from commit 1a62dd9895)
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Jani Nikula 2023-03-01 17:14:09 +02:00 • committed by Greg Kroah-Hartman

parent b15df140fe

commit 8d901a3363

1 changed files with 16 additions and 4 deletions

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drivers/gpu/drm/i915/display/icl_dsi.c

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