x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumeration from IBRS

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commit 7eb8956a7f upstream

The availability of the SPEC_CTRL MSR is enumerated by a CPUID bit on
Intel and implied by IBRS or STIBP support on AMD. That's just confusing
and in case an AMD CPU has IBRS not supported because the underlying
problem has been fixed but has another bit valid in the SPEC_CTRL MSR,
the thing falls apart.

Add a synthetic feature bit X86_FEATURE_MSR_SPEC_CTRL to denote the
availability on both Intel and AMD.

While at it replace the boot_cpu_has() checks with static_cpu_has() where
possible. This prevents late microcode loading from exposing SPEC_CTRL, but
late loading is already very limited as it does not reevaluate the
mitigation options and other bits and pieces. Having static_cpu_has() is
the simplest and least fragile solution.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

This commit is contained in:

Thomas Gleixner 2018-05-10 19:13:18 +02:00 • committed by Greg Kroah-Hartman

parent b1d1984f38

commit 8e0836d141

4 changed files with 21 additions and 9 deletions

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2

arch/x86/include/asm/cpufeatures.h

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18

arch/x86/kernel/cpu/bugs.c

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9

arch/x86/kernel/cpu/common.c

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1

arch/x86/kernel/cpu/intel.c

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