drm/amd/display: Fix DCFCLK and SOCCLK not set

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[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.

[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

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Ilya Bakoulin 2019-03-28 14:43:29 -04:00 • committed by Alex Deucher

parent 0213541d4b

commit 8e27a2d4cd

1 changed files with 4 additions and 0 deletions

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

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