i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

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On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.

Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

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Chew, Chiau Ee 2014-03-11 19:33:45 +08:00 • committed by Wolfram Sang

parent 4fda99627d

commit 8efd1e9ee3

1 changed files with 28 additions and 0 deletions

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drivers/i2c/busses/i2c-designware-pcidrv.c

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