clk: thead: support changing DPU pixel clock rate

Browse source

The DPU pixel clock rate corresponds to the required dot clock of the
display mode, so it needs to be tweakable.

Add support to change it, by adding generic divider setting code,
arming the code to the dpu0/dpu1 clocks, and setting the pixel clock
connected to the DPU (after a gate) to CLK_SET_RATE_PARENT to propagate
it to the dividers.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>

...

This commit is contained in:

Icenowy Zheng 2025-08-16 17:11:12 +08:00 • committed by Drew Fustini

parent 56a48c1833

commit 8fede7ff69

1 changed files with 58 additions and 5 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

63

drivers/clk/thead/clk-th1520-ap.c

View file