drm/meson: gate px_clk when setting rate

Browse source

[ Upstream commit 5c9837374e ]

Disable the px_clk when setting the rate to recover a fully
configured and correctly reset VCLK clock tree after the rate
is set.

Fixes: 77d9e1e6b8 ("drm/meson: add support for MIPI-DSI transceiver")
Reviewed-by: Nicolas Belin <nbelin@baylibre.com>
Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-4-99ecdfdc87fc@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-4-99ecdfdc87fc@linaro.org
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Neil Armstrong 2024-04-03 09:46:35 +02:00 • committed by Greg Kroah-Hartman

parent 22432baba4

commit 900d54bced

1 changed files with 7 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

7

drivers/gpu/drm/meson/meson_dw_mipi_dsi.c

View file