drm/amd/display: Move wait for hpd ready out from edp power control.

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It may take over 200ms for wait hpd ready. To optimize the resume time,
we can power on eDP in init_hw, wait for hpd ready when doing link
training.

also create separate eDP enable function to make sure eDP is powered up
before doing and DPCD access, as HPD low will result in DPDC transaction
failure.

After optimization,
setpowerstate 145ms -> 9.8ms,
DPMS 387ms -> 18.9ms

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Yongqiang Sun 2017-11-24 16:31:03 -05:00 • committed by Alex Deucher

parent 73da927b08

commit 904623ee59

7 changed files with 36 additions and 39 deletions

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25

drivers/gpu/drm/amd/display/dc/core/dc_link.c

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11

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

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15

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

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16

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

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4

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h

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3

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

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1

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

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