drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled

Browse source

CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.

v2: Use atomic refcount for get_power, put_power so that we can
    call each once(Abhay).
v3: Reset power well 2 to avoid any transaction on iDisp link
    during cdclk change(Abhay).
v4: Remove Power well 2 reset workaround(Ville).
v5: Remove unwanted Power well 2 register defined in v4(Abhay).
v6:
- Use a dedicated flag instead of state->modeset for min CDCLK changes
- Make get/put audio power domain symmetric
- Rebased on top of intel_wakeref tracking changes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Tested-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190320135439.12201-1-imre.deak@intel.com

...

This commit is contained in:

Ville Syrjälä 2019-03-20 15:54:36 +02:00 • committed by Imre Deak

parent 4c6ce5c990

commit 905801fe72

5 changed files with 86 additions and 23 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

3

drivers/gpu/drm/i915/i915_drv.h

View file

64

drivers/gpu/drm/i915/intel_audio.c

View file

30

drivers/gpu/drm/i915/intel_cdclk.c

View file

9

drivers/gpu/drm/i915/intel_display.c

View file

3

drivers/gpu/drm/i915/intel_drv.h

View file