irqchip/gic-v4.1: Ensure mutual exclusion betwen invalidations on the same RD

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The GICv4.1 spec says that it is CONTRAINED UNPREDICTABLE to write to
any of the GICR_INV{LPI,ALL}R registers if GICR_SYNCR.Busy == 1.

To deal with it, we must ensure that only a single invalidation can
happen at a time for a given redistributor. Add a per-RD lock to that
effect and take it around the invalidation/syncr-read to deal with this.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200304203330.4967-6-maz@kernel.org

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Marc Zyngier 2020-03-04 20:33:12 +00:00

parent b978c25f6e

commit 9058a4e980

3 changed files with 8 additions and 0 deletions

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6

drivers/irqchip/irq-gic-v3-its.c

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1

drivers/irqchip/irq-gic-v3.c

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1

include/linux/irqchip/arm-gic-v3.h

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