arm64: errata: add workaround for cortex-a53 erratum #845719

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When running a compat (AArch32) userspace on Cortex-A53, a load at EL0
from a virtual address that matches the bottom 32 bits of the virtual
address used by a recent load at (AArch64) EL1 might return incorrect
data.

This patch works around the issue by writing to the contextidr_el1
register on the exception return path when returning to a 32-bit task.
This workaround is patched in at runtime based on the MIDR value of the
processor.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

...

This commit is contained in:

Will Deacon 2015-03-23 19:07:02 +00:00

parent cc3979b54d

commit 905e8c5dca

4 changed files with 51 additions and 1 deletions

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21

arch/arm64/Kconfig

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3

arch/arm64/include/asm/cpufeature.h

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8

arch/arm64/kernel/cpu_errata.c

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20

arch/arm64/kernel/entry.S

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