clk: rockchip: add clock type for pll clocks and pll used on rk3066

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All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to
handle their plls:
                       |--\
xin32k ----------------|mux\
xin24m -----| pll |----|pll|--- pll output
       \---------------|src/
                       |--/

The pll output is sourced from 1 of 3 sources, the actual pll being one of
them. To change the pll frequency it is imperative to remux it to another
source beforehand. This is done by adding a clock-listener to the pll that
handles the remuxing before and after the rate change.

The output mux is implemented as a separate clock to make use of already
existing common-clock features for disabling the pll if one of the other
two sources is used.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

...

This commit is contained in:

Heiko Stübner 2014-07-03 01:59:10 +02:00 • committed by Mike Turquette

parent a245fecbb8

commit 90c5902540

4 changed files with 541 additions and 0 deletions

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1

drivers/clk/rockchip/Makefile

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431

drivers/clk/rockchip/clk-pll.c

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35

drivers/clk/rockchip/clk.c

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74

drivers/clk/rockchip/clk.h

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