clk: tegra: pll: Add pre/post rate-change hooks

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There is a need to temporarily re-parent CCLK away from PLLX if PLLX's
rate is about to change. The newly introduced PLL pre/post rate-change
hooks allow to handle such case.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
Tested-by: Jasper Korten <jja2000@gmail.com>
Tested-by: David Heidelberg <david@ixit.cz>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2020-03-19 22:02:19 +03:00 • committed by Thierry Reding

parent 1641567920

commit 9157abe74b

2 changed files with 17 additions and 1 deletions

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12

drivers/clk/tegra/clk-pll.c

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6

drivers/clk/tegra/clk.h

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