drm/i915: Use Engine1 instance for gen11 pm interrupts

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With gen11 the interrupt registers are shared between 2 engines,
with Engine1 instance being upper word and Engine0 instance being
lower. Annoyingly gen11 selected the pm interrupts to be in the
Engine1 instance.

Rectify the situation by shifting the access accordingly,
based on gen.

v2: comments, warn on overzealous rps_events

Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=108059
Testcase: igt/i915_pm_rps@min-max-config-loaded
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190410105923.18546-6-mika.kuoppala@linux.intel.com

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This commit is contained in:

Mika Kuoppala 2019-04-10 13:59:22 +03:00 • committed by Chris Wilson

parent 1071d0f687

commit 917dc6b53c

2 changed files with 43 additions and 18 deletions

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56

drivers/gpu/drm/i915/i915_irq.c

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5

drivers/gpu/drm/i915/i915_reg.h

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