openrisc: use shadow registers to save regs on exception

Browse source

Previously, the area between 0x0-0x100 have been used as a "scratch"
memory area to temporarily store regs during exception entry. In a
multi-core environment, this will not work.

This change is to use shadow registers for nested context.

Currently only the "critical" temp load/stores are covered, the
EMERGENCY_PRINT ones are left as is (when they are used, it's game over
anyway), they need to be handled as well in the future.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Stafford Horne <shorne@gmail.com>

...

This commit is contained in:

Stefan Kristiansson 2014-05-11 12:08:37 +03:00 • committed by Stafford Horne

parent ddc92bec6d

commit 91993c8c2e

2 changed files with 80 additions and 26 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

11

arch/openrisc/Kconfig

View file

95

arch/openrisc/kernel/head.S

View file