drm/i915/display: Add helper function for fuzzy clock check

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The hard coded clock rate stored in the PLL state will be removed by
a follow-up change. The clock is calculated instead of
using clock from the PLL divider values. Since this calculated clock
may vary due to fixed point rounding issues, a +-1 kHz variation is
allowed with the request clock rate against the calculated clock rate.

v2:
- Use the stricter +-1 kHz allowed difference.
- Derive the clock from PLL dividers in intel_cx0pll_enable().
- Move corresponding fuzzy check for LT PHY PLLs to this patch.

v3: Reword commit message (Suraj)
    Move clock check to intel_dpll and rename it (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-9-mika.kahola@intel.com

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This commit is contained in:

Mika Kahola 2026-01-19 09:37:49 +00:00

parent cf0635d40a

commit 920fa5d920

4 changed files with 30 additions and 5 deletions

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22

drivers/gpu/drm/i915/display/intel_cx0_phy.c

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5

drivers/gpu/drm/i915/display/intel_dpll.c

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1

drivers/gpu/drm/i915/display/intel_dpll.h

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7

drivers/gpu/drm/i915/display/intel_lt_phy.c

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