From 923bab365da28fdae995d08e67fbc2aa3eff1c6c Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Thu, 24 Sep 2026 14:08:42 -0700 Subject: [PATCH] Revert "drm/xe: Set mask bits for CCS_MODE register" This reverts commit 23ea2c7572d4735ef66beb1e4feb8ae510b78247. A recent bspec update dropped the details about CCS_MODE being a masked register (i.e., bits [15:0] are only updated by register writes when the corresponding bit in [31:16] mask is also set by the write) on Xe2 and later. Apparently the documented mask bits were never actually implemented in hardware, so all register writes will update all bits of [15:0], just as the register behaved on Xe1 platforms. Setting the non-existent mask bits in Xe didn't have any negative impact since none of our existing code was trying to use the mask to limit which bits were updated. However this could have caused problems in the future if we ever rework this code in a way that tried to rely on the masking behavior. Update the register definition and drop the use of the mask to align with the new bspec definition and avoid potential mistakes in the future. Bspec: 55887 Cc: Balasubramani Vivekanandan Reviewed-by: Daniel Charles Link: https://patch.msgid.link/20260924-ccs_mode_drop_mask-v1-1-5b2b35708b83@intel.com Signed-off-by: Matt Roper --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +- drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 2e059cb36c82..926b14e32c40 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -636,7 +636,7 @@ * [4-6] RSVD * [7] Disabled */ -#define CCS_MODE XE_REG(0x14804, XE_REG_OPTION_MASKED) +#define CCS_MODE XE_REG(0x14804) #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c index baee1f4a6b01..224a15675203 100644 --- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c +++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c @@ -70,12 +70,6 @@ static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) } } - /* - * Mask bits need to be set for the register. Though only Xe2+ - * platforms require setting of mask bits, it won't harm for older - * platforms as these bits are unused there. - */ - mode |= CCS_MODE_CSLICE_0_3_MASK << 16; xe_mmio_write32(>->mmio, CCS_MODE, mode); xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",