diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 8fc89fb6eef1..9d36283efe0f 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -406,6 +406,9 @@ ext_sram: sram@2,0 { compatible = "mmio-sram"; reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 2 0 0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi index c4422f587055..707d22a219d8 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi @@ -24,16 +24,25 @@ sram0: sram@10000000 { compatible = "mmio-sram"; reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram1: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram2: sram@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi index 72f12db8d53a..d138ee7869ff 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi @@ -24,16 +24,25 @@ sram0: sram@10000000 { compatible = "mmio-sram"; reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram1: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram2: sram@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; };