clk: imx7d: fix ahb clock mux 1

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The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in  Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.

While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

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Stefan Agner 2016-04-28 14:07:03 -07:00 • committed by Shawn Guo

parent 585a60f24b

commit 92a847e360

1 changed files with 1 additions and 1 deletions

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drivers/clk/imx/clk-imx7d.c

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