drm/i915: HSW PM Frequency bits fix

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According to HSW PM programming guide, frequency bits starts at
24 instead of 25.

v2: Paulo Zanoni noticed that only frequency bits can be set at
GEN6_RPNSWREQ. All others are read only.

CC: Ben Widawsky <ben@bwidawsk.net>
CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Rodrigo Vivi 2013-03-25 17:55:49 -03:00 • committed by Daniel Vetter

parent a42f704b71

commit 92bd1bf089

2 changed files with 22 additions and 10 deletions

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1

drivers/gpu/drm/i915/i915_reg.h

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31

drivers/gpu/drm/i915/intel_pm.c

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