RISC-V: KVM: Cleanup stale TLB entries when host CPU changes

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On RISC-V platforms with hardware VMID support, we share same
VMID for all VCPUs of a particular Guest/VM. This means we might
have stale G-stage TLB entries on the current Host CPU due to
some other VCPU of the same Guest which ran previously on the
current Host CPU.

To cleanup stale TLB entries, we simply flush all G-stage TLB
entries by VMID whenever underlying Host CPU changes for a VCPU.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>

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Anup Patel 2022-05-09 10:44:11 +05:30 • committed by Anup Patel

parent 13acfec2db

commit 92e450507d

3 changed files with 39 additions and 0 deletions

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5

arch/riscv/include/asm/kvm_host.h

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23

arch/riscv/kvm/tlb.c

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11

arch/riscv/kvm/vcpu.c

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