clk: samsung: exynosautov9: fix wrong pll clock id value

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[ Upstream commit 04ee3a0b44 ]

All PLL id values of CMU_TOP were incorrectly set to FOUT_SHARED0_PLL.
It modified to the correct PLL clock id value.

Fixes: 6587c62f69 ("clk: samsung: add top clock support for Exynos Auto v9 SoC")
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240328091000.17660-1-jaewon02.kim@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Jaewon Kim 2024-03-28 18:10:00 +09:00 • committed by Greg Kroah-Hartman

parent e08f0cc0af

commit 9302afe52d

1 changed files with 4 additions and 4 deletions

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drivers/clk/samsung/clk-exynosautov9.c

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