clk: tegra: Fix pll_a1 iddq register, add pll_a1

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pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add
pll_a1 to the set of clocks defined for Tegra210.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Peter De Schrijver 2017-02-23 12:44:38 +02:00 • committed by Thierry Reding

parent c1ae3cfa0e

commit 9326947f22

1 changed files with 2 additions and 1 deletions

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drivers/clk/tegra/clk-tegra210.c

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