From 934b9973f712484af9ae8876533d9992fc59cc93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 26 Aug 2026 16:40:24 +0300 Subject: [PATCH] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so we are currently forcing the voltage level to 3 all the time on DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid this. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260826134033.13976-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4c093d84da0d..b9e13e40fec5 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2647,7 +2647,6 @@ static void intel_pcode_notify(struct intel_display *display, update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, - SKL_CDCLK_PREPARE_FOR_CHANGE | update_mask, SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, 3);