MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions

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MIPS R6 changed the 'cache' instruction opcode and reduced the
offset field to 8 bits. This means we now have to adjust the
base register every 256 bytes and as a result of which we can
no longer use the previous cache functions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

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Markos Chandras 2014-11-13 13:25:51 +00:00

parent 8716a76356

commit 934c79231c

1 changed files with 148 additions and 2 deletions

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arch/mips/include/asm/r4kcache.h

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