Allwinner clock changes for 5.2

Our usual bunch of changes, this time, it's mainly:
 
   - Export a new clock for the MBUS controller on the A13
   - H6 fixes to support a finer clocking of the video and VPU engines
   - Add some Kconfig options
   - Some bit offset fixes
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Merge tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clk driver updates from Maxime Ripard:

Our usual bunch of changes, this time, it's mainly:

 - Export a new clock for the MBUS controller on the A13
 - H6 fixes to support a finer clocking of the video and VPU engines
 - Add some Kconfig options
 - Some bit offset fixes

* tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun5i: Export the MBUS clock
  clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
  clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
  clk: sunxi-ng: h6: Preset hdmi-cec clock parent
  clk: sunxi: Add Kconfig options
  clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
  clk: sunxi-ng: Allow DE clock to set parent rate
This commit is contained in:
Stephen Boyd 2019-04-19 13:11:39 -07:00
commit 93737fe93e
10 changed files with 95 additions and 36 deletions