arm64: tegra: Fix base address for SOR1 on Tegra194

Browse source

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>

...

This commit is contained in:

Thierry Reding 2019-07-26 12:16:18 +02:00

parent 1aaa769867

commit 939e7430de

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

arch/arm64/boot/dts/nvidia/tegra194.dtsi

View file