clk: sunxi-ng: Support fixed post-dividers on MP style clocks

Browse source

On the A64, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.

To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.

To do this, we first add fixed post-divider to the MP style clocks,
which the MMC module clocks are.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

...

This commit is contained in:

Chen-Yu Tsai 2017-12-04 13:19:11 +08:00 • committed by Maxime Ripard

parent 4d1369cae0

commit 946797aa3f

2 changed files with 42 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

20

drivers/clk/sunxi-ng/ccu_mp.c

View file

24

drivers/clk/sunxi-ng/ccu_mp.h

View file