drm/i915: Set aux clk to 100MHz for Valleyview

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Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Vijay Purushothaman 2012-09-27 19:13:01 +05:30 • committed by Daniel Vetter

parent 3bcedbe5f2

commit 9473c8f485

1 changed files with 7 additions and 1 deletions

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drivers/gpu/drm/i915/intel_dp.c

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