media: ccs-pll: Add support flexible OP PLL pixel clock divider

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Flexible OP PLL pixel clock divider allows a higher OP pixel clock than
what the bus can transfer. This generally makes it easier to select pixel
clock dividers.

This changes how the pixel rate on the bus and minimum VT divisor are
calculated, as the pixel rate is no longer directly determined by the
OP pixel clock and the number of the lanes.

Also add a sanity check for sensors that do not support flexible OP PLL
pixel clock divider. This could have caused the PLL calculator to come up
with an invalid configuration for those devices.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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This commit is contained in:

Sakari Ailus 2020-08-07 11:07:14 +02:00 • committed by Mauro Carvalho Chehab

parent c4c0b22272

commit 9490a2279f

3 changed files with 23 additions and 8 deletions

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26

drivers/media/i2c/ccs-pll.c

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1

drivers/media/i2c/ccs-pll.h

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4

drivers/media/i2c/ccs/ccs-core.c

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