drm/amd/display: Reset steer fifo before unblanking the stream

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[why]
During mode transition steer fifo could overflow. Quite often it
recovers by itself, but sometimes it doesn't.

[how]
Add steer fifo reset before unblanking the stream. Also add a short
delay when resetting dig resync fifo to make sure register writes
don't end up back-to-back, in which case the HW might miss the reset
request.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nikola Cornij 2019-11-11 18:03:59 -05:00 • committed by Alex Deucher

parent 084e1de7b9

commit 949ffc8b36

1 changed files with 10 additions and 2 deletions

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drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c

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