clk: at91: clk-master: Add check for divide by 3

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[ Upstream commit e0237f5635 ]

A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Ryan Wanner 2025-09-08 13:07:17 -07:00 • committed by Greg Kroah-Hartman

parent 74c0381f99

commit 94a649487e

1 changed files with 3 additions and 0 deletions

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drivers/clk/at91/clk-master.c

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