clk: meson: remove unnecessary rounding in the pll clock

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The pll driver performs the rate calculation in Mhz, which adds an
unnecessary rounding down to the Mhz of the rate. Use 64bits long
integers to perform this calculation safely on meson8b and perform the
calculation in Hz instead

Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Jerome Brunet 2018-01-19 16:55:23 +01:00

parent 4ed98e9572

commit 94aa8a41f1

1 changed files with 9 additions and 8 deletions

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drivers/clk/meson/clk-pll.c

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