drm/amd/display: ensure EASF and ISHARP coefficients are programmed together

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[Why]
EASF coefficients are programmed to RAM and then RAM selector is toggled.
 ISHARP coefficients are programmed after so they will not be in the same
 RAM block

[How]
Move ISHARP programming before EASF programming
Add flag if ISHARP coefficients are updated.  If so, then
 force EASF coefficients programming

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Samson Tam <samson.tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Samson Tam 2024-07-10 17:09:04 -04:00 • committed by Alex Deucher

parent 0cf8050691

commit 94beb4ac1b

1 changed files with 20 additions and 8 deletions

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drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

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