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drm/amdkfd: set CP_IQ_WAIT_TIME2.QUE_SLEEP on GFX 12.1
The optimized QUE_SLEEP was only programmed on the HWS packet-manager path via a PM4 WRITE_DATA packet, which is skipped when MES is enabled. Add gfx12.1 get_iq_wait_times/build_dequeue_wait_counts_packet_info callbacks and program CP_IQ_WAIT_TIME2 through the MES WRITE_REG op at start_cpsch, per XCC. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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