drm/amd/display: Update clock table to include highest clock setting

Browse source

[ Upstream commit 2d99a7ec25 ]

[Why]
Currently, the clk manager matches SocVoltage with voltage from
fused settings (dfPstate clock table). And then corresponding clocks
are selected.

However in certain situations, this leads to clk manager not
including at least one entry with highest supported clock setting.

[How]
Update the clk manager to include at least one entry with highest
supported clock setting.

Reviewed-by: Pavle Kotarac <pavle.kotarac@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Swapnil Patel <Swapnil.Patel@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Swapnil Patel 2023-03-01 14:33:33 -05:00 • committed by Greg Kroah-Hartman

parent 5ff443728d

commit 9519b377f6

1 changed files with 18 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

19

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c

View file