MX35: Fix bogus L2 cache settings

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i.MX35 CPUs marked with "MCIMX357CJQ5C M99V CTHA0943B" are coming with bogus
L2 cache settings. If these settings are kept unmodified prior enabling the L2
cache the CPU runs amok immediately when its enabled.

This fix should not hurt already working CPUs, as they are using the written
register value already.

Its currently unknown if its possible to detect the production lot from the
software to fix only affected CPUs.

While at it, make sure that mxc_init_l2x0 is only executed on i.MX31/35

Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

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Juergen Beisert 2010-09-22 09:42:15 +02:00 • committed by Sascha Hauer

parent 55fd2ef6d9

commit 9524705c86

1 changed files with 18 additions and 0 deletions

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arch/arm/mach-mx3/mm.c

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