drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl

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Latency programming remains same as that of ICL and
setting latency otimization for PCS_DW1 lanes is same as
that of EHL, hence extending it to TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-3-vandita.kulkarni@intel.com

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Vandita Kulkarni 2019-07-30 13:06:44 +05:30 • committed by Uma Shankar

parent 3522a33a27

commit 960e9836f7

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/i915/display/icl_dsi.c

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