From 968b69dd7983c737d6bec7568a6d03a807cf1e12 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 2 Aug 2026 11:25:48 -0500 Subject: [PATCH] drm/amd/display: Promote DC to 3.2.393 This DC patchset brings improvements in multiple areas. In summary, we have: * DCN6 fixes on GPUVM calculations, HostVM and SOCBB VM config, clkmgr interfaces, and peak bandwidth measurement * HDMI FRL fixes on LT timeout behaviour and cap restore during non-destructive link verify * Greatly enhanced KUnit coverage across CRTC, VRR, and cursor paths * eDP panel polarity control, FreeSync range quirk, and Z8-based zstate support * DCE ASIC code gated behind CONFIG_DRM_AMD_DC_DCE for DCN-only builds * Fixes on HPD filter programming, DMUB DIG PHY wait, dcn42b force_min_dcfclk clamp, audio tests, and UTM client QC profile override Acked-by: Wayne Lin Signed-off-by: Taimur Hassan Signed-off-by: Tom Chung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 34d4ede12e79..c23299d3f36a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -66,7 +66,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.392" +#define DC_VER "3.2.393" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC