x86, cpu: Package Level Thermal Control, Power Limit Notification definitions

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Add package level thermal and power limit feature support.

The two MSRs and features are new starting with Intel's Sandy Bridge processor.

Please check Intel 64 and IA-32 Architectures SDMV Vol 3A 14.5.6 Power Limit
Notification and 14.6 Package Level Thermal Management.

This patch also fixes a bug which defines reverse THERM_INT_LOW_ENABLE bit and
THERM_INT_HIGH_ENABLE bit.

[ hpa: fixed up against current tip:x86/cpu ]

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
LKML-Reference: <1280448826-12004-2-git-send-email-fenghua.yu@intel.com>
Reviewed-by: Len Brown <len.brown@intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

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This commit is contained in:

Fenghua Yu 2010-07-29 17:13:42 -07:00 • committed by H. Peter Anvin

parent a5b91606bd

commit 9792db6174

3 changed files with 19 additions and 2 deletions

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2

arch/x86/include/asm/cpufeature.h

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17

arch/x86/include/asm/msr-index.h

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2

arch/x86/kernel/cpu/scattered.c

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