drm/i915/color: Add CSC on SDR plane color pipeline

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Add the fixed-function CSC block to color pipeline in SDR planes
as a DRM_COLOROP_FIXED_MATRIX colorop.

v2:
- s/DRM_COLOROP_FM_YCBCR2020_FULL_RGB_NC/
	DRM_COLOROP_FM_YCBCR2020_NC_FULL_RGB
- Inline icl_is_hdr_plane() instead of storing in local variable

v3:
- In preparation of a simple pipeline
	[YUV Full/Limited -> RGB]
  Make the Fixed Matrix ColorOp support Limited Range enums
  (DRM_COLOROP_FM_YCBCRXXX_LIMITED_RGB) too.
- Therefore s/sdr_plane_pipeline/sdr_plane_yuv_pipeline

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260902075417.656673-2-chaitanya.kumar.borah@intel.com

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This commit is contained in:

Chaitanya Kumar Borah 2026-09-02 13:24:09 +05:30

parent a4c0e7f804

commit 985bc8ee61

2 changed files with 23 additions and 1 deletions

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23

drivers/gpu/drm/i915/display/intel_color_pipeline.c

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1

drivers/gpu/drm/i915/display/intel_display_limits.h

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