clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI

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Add clock and reset entries for the DRP-AI block, which is available only
on the Renesas RZ/V2L SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-01-06 20:28:53 +00:00 • committed by Geert Uytterhoeven

parent 5599c7c4b4

commit 989d673ff7

2 changed files with 55 additions and 2 deletions

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55

drivers/clk/renesas/r9a07g044-cpg.c

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2

drivers/clk/renesas/rzg2l-cpg.h

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