net/mlx4_en: Align tx path structures to cache lines

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Reorganize struct mlx4_en_tx_ring to have:
- One cache line containing last_nr_txbb & cons & wake_queue, used by tx
  completion.
- One cache line containing fields dirtied by mlx4_en_xmit()
- Following part is read mostly and shared by cpus.

Align struct mlx4_en_tx_info to a cache line

Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Eric Dumazet 2014-10-05 12:35:10 +03:00 • committed by David S. Miller

parent 7dfa4b414d

commit 98b1634941

1 changed files with 46 additions and 40 deletions

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86

drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

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