drm/i915: Program DPLL P1 dividers consistently

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On g4x and pch the DPLL has two P1 dividers (for refresh rate
switching). Program the FPx1 P1 divider consistently to the reduced
clock P1 divider if available, otherwise just program it to the
same value as the FPx0 P1 divider.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210715093530.31711-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

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Ville Syrjälä 2021-07-15 12:35:25 +03:00

parent 510e890e82

commit 98b27e7989

1 changed files with 41 additions and 39 deletions

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drivers/gpu/drm/i915/display/intel_dpll.c

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