clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro

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Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
mentioned in the hardware manual(Rev.1.00 Sep, 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-12-03 11:51:49 +00:00 • committed by Geert Uytterhoeven

parent 24aaff6a6c

commit 98ee8b2f66

1 changed files with 2 additions and 2 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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