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x86/ibt: Add IBT feature, MSR and #CP handling

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The bits required to make the hardware go.. Of note is that, provided
the syscall entry points are covered with ENDBR, #CP doesn't need to
be an IST because we'll never hit the syscall gap.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20220308154318.582331711@infradead.org
This commit is contained in:
Peter Zijlstra 2022-03-08 16:30:35 +01:00
commit 991625f3dd
9 changed files with 133 additions and 2 deletions
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