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amd-xgbe: Prepare for more fine grained cache coherency controls

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In prep for setting fine grained read and write DMA cache coherency
controls, allow specific values to be used to set the cache coherency
registers.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Lendacky, Thomas 2017-06-28 13:43:09 -05:00 • committed by David S. Miller
commit 9916716a1b
5 changed files with 14 additions and 67 deletions
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