drm/amdgpu/gfx9: set additional bits on CP halt

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Need to set the pipe reset and cache invalidation bits
on halt otherwise we can get stale state if the CP firmware
changes (e.g., on module unload and reload).

Reviewed-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Alex Deucher 2024-09-16 13:16:53 -04:00

parent 37b993225d

commit 993fcc40ae

1 changed files with 18 additions and 1 deletions

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19

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

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