drm/amd/display: dp interlace MSA timing programming for Interlace mode.

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[Why]
DP compliance box shows wrong MSA data.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Charlene Liu 2018-12-19 13:47:19 -05:00 • committed by Alex Deucher

parent 570744b98c

commit 9983b80053

2 changed files with 77 additions and 56 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

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65

drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c

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68

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

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