KVM: arm64: Add handling of AArch32 PCMEID{2,3} PMUv3 registers

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Despite advertising support for AArch32 PMUv3p1, we fail to handle
the PMCEID{2,3} registers, which conveniently alias with the top
bits of PMCEID{0,1}_EL1.

Implement these registers with the usual AA32(HI/LO) aliasing
mechanism.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>

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This commit is contained in:

Marc Zyngier 2020-12-31 11:39:01 +00:00

parent cb95914685

commit 99b6a4013f

1 changed files with 9 additions and 3 deletions

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arch/arm64/kvm/sys_regs.c

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